1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly, to a semiconductor memory device of a multilayer metal interconnection line structure. More particularly, the present invention relates to a configuration for a word line of an embedded memory integrated with a logic circuit on the same semiconductor substrate.
2. Description of the Background Art
FIG. 17A is a diagram schematically showing an arrangement of array mats (memory mats) of a conventional DRAM (dynamic random access memory). In FIG. 17A, the DRAM includes four memory mats MM0 to MM3 placed in respective regions of four quartered regions on a semiconductor chip CH. Memory mats MM0 to MM3 each have a storage capacity of 16 M bits, for example, with a total storage capacity of 64 M bits.
A peripheral circuit PH0 is placed in a region between memory mats MM0 and MM2 and memory mats MM1 and MM3, a peripheral circuit PH1 is placed in a region between memory mats MM0 and MM2, and a peripheral circuit PH2 is placed in a region between memory mats MM1 and MM3. Peripheral circuit PH0 includes a peripheral control circuit that controls operations of memory mats MM0 to MM3, for example. Peripheral circuits PH1 and PH2 each include a data input/output circuit and an address input circuit, for example. Peripheral circuits PH1 and PH2 may further include local control circuits controlling operations of corresponding memory mats MM0 to MM3 according to a control signal from a main control circuit included in peripheral circuit PH0.
By placing memory mats MM0 to MM3 in four quartered regions on semiconductor chip CH separately, lengths of word lines and bit lines included in each of memory mats MM0 to MM3 are reduced to decrease a time required for selection of a memory cell and data transfer.
FIG. 17B is a diagram schematically showing an example of a configuration of memory mats MM0 to MM3 shown in FIG. 17A. Since each of memory mats MM0 to MM3 has the same configuration with others, an arrangement in one memory mat MM is shown in FIG. 17B. In FIG. 17B, memory mat MM is divided into 16 sub blocks SUB by word line shunt regions SHT in a row direction, while being divided into 32 sub blocks SUB by sense amplifier bands SAB in a column direction.
In a sub block UB, 256 word lines and 128 bit lines are placed, and therefore sub blocks UB has a storage capacity of 32 K bits.
A word line shunt region SHT is a region in which electrical connection is made between a highly resistive word line connected to gates of memory cell transistors and a low resistivity metal interconnection line ion line formed of aluminum or the like above the word line. By interconnecting the metal interconnection line ion line and the word line electrically, a resistance of the word line is reduced equivalently to transmit a word line drive signal to an end thereof at high speed.
In a sense amplifier band SAB, sense amplifier circuits are provided corresponding to respective bit line pairs. A sense amplifier circuit is shared between bit line pairs of sub blocks adjacent to each other in the column direction.
A column decoder CD is provided to memory mat MM. Activation of a sub block is performed with sub blocks SUB aligned in the row direction being a unit. A column select signal from column decoder CD is applied commonly to sub blocks SUB aligned in the column direction. Only a local internal data line provided to a sub block in a selected state is coupled to a global internal data line (IO line) according to a row block select signal, for example.
As shown in FIG. 17B, by dividing memory mat MM into sub blocks in the column direction, a length of a bit line pair is reduced to decrease a bit line load and implement a high speed sense operation. Furthermore, by providing a word line shunt region SHT, a word line is driven into a selected state at high speed as described below.
FIG. 18 is a diagram schematically showing arrangement of a word line for sub blocks SUB aligned in the row direction. A common word line WL is provided for sub blocks aligned in the row direction. Word line WL is driven by a word line driver. A word line shunt region SHT is arranged between adjacent sub blocks SUB.
FIG. 19 is a diagram schematically showing a configuration related to the word line shown in FIG. 18. In FIG. 19, a low resistivity metal interconnection line UPL is provided above and in parallel to word line WL. Metal interconnection line UPL and word line WL are both connected to a word driver WD. Metal interconnection line UPL and word line WL are electrically connected (short circuited) to each other through a contact CNT in shunt region SHT. In one sub block, a metal interconnection line UPL has a resistance r, while word line WL has a resistance R. A word line WL is generally made of polysilicon, and has a large resistance, similar to the gate of a memory cell transistor. In the case where a high resistance word line WL is driven by a word driver WD provided at one end of a memory mat, a long propagation delay arises in transmission of a word line drive signal to sub block UB farthest from word driver WD. Such a signal propagation delay disables high speed driving of a word line into a selected state.
In order to reduce propagation delay of a word line drive signal, a metal interconnection line UPL is provided in parallel to a word line WL in an upper layer thereof and electrically connected to word line WL through contacts CNT in shunt regions SHT. Such a structure in which a word line WL is electrically connected (short circuited) to a low resistivity metal interconnection line at a prescribed interval between adjacent connection points is called a word line shunting (strapping) structure. The metal interconnection line UPL has a low resistance value and therefore, causes a short signal propagation delay. By utilizing such a structure, a word line drive signal from a word driver WD is transmitted to the sub block at the farthest position at high speed to drive a word line into a selected state at high speed.
FIG. 20 is a diagram schematically showing another arrangement of array mats. In FIG. 20, a DRAM includes memory block regions MB0 to MB3 arranged in respective 4 quartered regions. A peripheral circuit PHA is placed between memory blocks MB0 and MB1 and memory blocks MB2 and MB3. A row decoder RD is placed between memory blocks MB0 and MB1 and another row decoder RD is placed between memory blocks MB2 and MB3.
Each of memory blocks MB0 to MB3 includes 4 memory sub arrays (memory mats) MRY0 to MRY3. Column decoders CD are provided corresponding to the respective memory sub arrays MRY0 to MRY3. An internal data line is placed between memory sub arrays MRY0 and MRY1, and an internal data line is placed between memory sub arrays MRY2 and MRY3.
The DRAM shown in FIG. 20 has a storage capacity of 512 M bits and each of memory block regions MB0 to MB3 has memory cells of 128 bits arranged therein. That is, each of memory sub arrays MRY0 to MRY3 has a storage capacity of 32 M bits.
In the DRAM shown in FIG. 20, each of memory sub arrays MRY0 to MRY3 is fabricated suppressing increase in an occupancy area thereof, with a design rule for a memory cell made small to miniaturize a memory transistor. However, a storage capacity of a memory mats (memory sub arrays) becomes as large as 32 M bit and a row select signal is transmitted from a row decoder disposed at one end of a memory block MB commonly to corresponding memory sub arrays MRY0 to MRY3, and therefore, a length of a word line becomes long, and it becomes impossible to meet a requirement of high speed operation even with the above word line shunt structure.
Furthermore, a similar arrangement of memory mats are also used in a DRAM having a storage capacity of 256 M bits and a storage capacity of each memory mats (memory sub arrays) is 16 M bits. In this case, with a storage capacity of one memory sub array MRY (MRY0 to MRY3) being 16 M bits, if a row decoder is provided between memory arrays, a configuration of memory mats becomes similar to the configuration shown in FIG. 17. Therefore, by use of the word line shunt structure, a propagation delay time of a word line drive signal can be reduced. However, in a 256 M bit DRAM, an even higher speed has been required as an operating condition, and therefore, a signal propagation delay time through a metal interconnection line UPL (see FIG. 19) in an upper layer cannot be neglected only with reduction in propagation delay of a word line drive signal using a word line shunt structure. Consequently, there is caused a situation in which the demand for high speed operation cannot be satisfied.
Instead of the word line shunt structure, a hierarchical word line drive scheme is utilized in order to drive a word line at even higher speed.
FIG. 21 is a diagram schematically showing a configuration related to a word line according to the hierarchical word drive scheme. In FIG. 21, one memory sub array is divided into plural memory sub blocks MSBK by sub word driver bands SWB. A main word line MWL is provided commonly to memory sub blocks MSBK aligned in the row direction. Sub word lines SWL are provided in each of memory sub blocks MSBK. Sub word lines SWL are provided corresponding to respective memory cell rows of a corresponding memory sub block MSBK and connected to memory cells on corresponding rows. A sub word line SWL is made of polysilicon, similar to a gate material of a memory cell transistor, and has a high resistivity.
In a sub word driver band SWB, sub word drivers SWD are provided corresponding to sub word lines. Sub word drivers SWD are provided to rows alternately in sub word driver bands on both sides of each memory sub block in order to alleviate a pitch condition on placement of the sub word drivers. A sub word driver SWD drives sub word lines SWL on adjacent two memory sub blocks MSBK to a selected state according to a signal on a corresponding main word line MWL and a sub decode signal.
A main word line is provided corresponding to a prescribed number of sub word lines and formed of a low resistivity metal interconnection line. Main word drivers MWD are provided corresponding to the respective main word lines, and a main word line drive signal from main word line driver MWD is transmitted onto a corresponding main word line MWL. That is, word lines are constructed in a hierarchical structure including main word lines driven by main word line drivers and sub word lines driven by sub word line drivers. Since memory cells are not connected to a main word line, a load resistance and a load capacitance of a main word line are small, thereby driving a main word line into a selected state at high speed. Furthermore, a sub word line SWL is provided only within a corresponding memory sub block and therefore, has a small number of memory cells connected thereto, to have a small load to be driven, thereby enabling a sub word line to be driven into a selected state at even higher speed.
FIG. 22 is a diagram specifically showing a configuration of a sub word driver band.
In FIG. 22, a sub word driver SWD is provided commonly to sub word lines in adjacent memory sub arrays on both sides of a sub word driver band SWB and drives a corresponding sub word line SWL into a selected state according to a signal on a corresponding main word line MWL and a sub decode signal, not shown. In FIG. 22, since sub word drivers SWD are provided to one in alternate rows in one sub word driver band SWB, sub word drivers SWDa and SWDc placed in respective sub word driver bands SWBa and SWBc each drive sub word lines in two memory sub blocks. In sub word driver band SWBb, no sub word driver is placed in alignment with sub word drivers SWDa and SWDc. In order to drive sub word lines provided on each of other rows, sub word drivers are placed in sub word driver band SWBb.
As shown in FIG. 22, word lines are organized in a hierarchical structure composed of main word lines MWL and sub word lines SWL, and main word lines MWL are formed of metal interconnection line with a small resistance, rm. Therefore, a main word line drive signal can be transmitted to an end of a selected main word line at high speed by main word driver MWD. Even if a resistance Rs of sub word line SWL is larger, compared with that of main word line MWL, a resistance of each sub word line is small since sub word lines are provided in units of memory sub blocks MSBK, thereby enabling a sub word line SWL to be driven into a selected state at high speed by sub word drivers (SWDa and SWDc). Particularly, main word driver MWD is only required to drive main word line MWL, thereby enabling a main word line drive signal to be transmitted up to the end of main word line MWL at high speed.
Hence, according to the hierarchical word drive scheme, since sub word drivers are placed in a distributed manner in a memory mat, a drive capability thereof for sub word line SWL can be increased, thereby enabling sub word line SWL to be driven into a selected state at high speed.
FIG. 23 is a diagram showing an example of a configuration of sub word driver SWD (SWDa and SWDc) shown in FIGS. 21 and 22. In FIG. 23, sub word driver SWD includes: a P channel MOS transistor (insulated gate field effect transistor) Q1 for transmitting sub decode signal SD onto sub word line SWL according to a main word line drive signal ZMWL on main word line MWL; an N channel MOS transistor Q2 coupling sub word line SWL to a ground node according to main word line drive signal ZMWL; and an N channel MOS transistor Q3 coupling sub word line SWL to the ground node according to a complementary sub decode signal ZSD. Main word line drive signal ZMWL is at L level when selected, and at H level when non-selected.
The reason why sub decode signals SD and ZSD are used in sub word driver SWD is as follows: One main word line MWL is provided for a prescribed number of, for example 4 or 8, sub word lines SWL. With such an arrangement, a pitch condition for main word lines is alleviated. One of the prescribed number of sub word lines SWL in one memory sub block MSBK is selected according to sub decode signals SD and ZSD. Sub decode signals SD and ZSD are complementary to each other.
When main word drive signal ZMWL is at H level, MOS transistor Q1 is in a non-conductive state, while MOS transistor Q2 is in a conductive state to couple sub word line SWL to the ground potential. In this case, sub word line SWL is kept in a non-selected state, independently of logic levels of sub decode signals SD and ZSD.
When main word line drive signal ZMWL is at L level and sub decode signal SD is at H level, MOS transistor Q1 becomes conductive to transmit sub decode signal SD at H level onto sub word line SWL and drive sub word line SWL into a selected state. At this time, complementary sub decode signal ZSD is at L level and MOS transistor Q3 is in a non-conductive state.
When main word line drive signal ZMWL goes to L level, MOS transistor Q2 enters a non-conductive state. When sub decode signal SD is at L level, MOS transistor Q1 has the gate and source thereof at the same voltage level to enter a non-conductive state. At this time, complementary sub decode signal ZSD is at H level to cause MOS transistor Q3 to be conductive and keep sub word line SWL at the ground voltage level. That is, when main word line drive signal ZMWL is at L level and sub decode signal SD is at L Level, MOS transistors Q1 and Q2 both enter a non-conductive state and therefore, MOS transistor Q3 is caused to be in a conductive state using complementary sub decode signal ZSD in order to prevent the sub word line from entering a floating state, to raise the non-selected sub word lines at a potential level above ground potential level reliably.
Since sub word line driver SWD has plural MOS transistors, an occupancy area of a sub word driver is larger, compared with a structure such as a word line shunt structure in which a metal interconnection line is connected to word line WL with a contact. For this reason, the number of sub word driver bands SWB is restricted to be lower than the number of word line shunt regions and the number of memory sub blocks MSBK is less than the number of memory sub blocks UB in the word line shunt structure.
In the hierarchical word line drive scheme using sub word drivers SWD, although a layout area of sub word driver bands SWD becomes larger, a drive capability for sub word lines increases, and therefore, the number of memory sub arrays obtained by division of a memory array is reduced, thereby balancing a trade-off between increase in operating speed and suppression of increase in layout area.
In order to reduce total power consumption of a system, realize a high speed operation and size down the system, there has been adopted a system LSI to construct one system on one semiconductor chip. As a semiconductor memory device which is applied to such a system LSI, a logic merged memory (eRAM; embedded RAM) is available.
FIG. 24 is a diagram schematically showing an example of a configuration of a conventional logic merged memory. In FIG. 24, the logic merged memory includes a logic circuit LG and a memory circuit MK integrated on a semiconductor chip CHI. Logic circuit LG and memory circuit MK are interconnected by on-chip internal interconnection lines IL. Memory circuit MK is constituted of a DRAM. Logic circuit LG performs transmission/reception of data with an external device and memory circuit MK can be accessed only by logic circuit LG (in a normal operation). In the normal operation, the external device cannot access memory circuit MK directly.
In this logic merged memory, logic circuit LG and memory circuit MK are interconnected by on-chip internal interconnection lines IL. Internal connection line IL is of a small load, thereby enabling a high speed transfer of a signal/data between logic circuit LG and memory circuit MK. Furthermore, since internal interconnection line IL is on-chip interconnection line, a data line transmitting data can be formed at an internal interconnection pitch without receiving an influence of a pitch condition on pin terminals. Therefore, a bit width of data transferred between logic circuit LG and memory circuit MK can be extended, thereby enabling a band width of data transfer to be extended. Accordingly, even with a high operating frequency of logic circuit LG, logic circuit LG can access memory circuit MK to receive necessary data therefrom to execute a prescribed process.
Furthermore, since logic circuit LG and memory circuit MK are integrated on the same semiconductor chip CHI, a system size is reduced, as compared with a case where logic circuit LG and memory circuit MK are separately mounted on a board.
In system LSI including the logic merged memory, other analog core circuits and other memories such as SRAM (static random access memory) and so on may be mounted on semiconductor chip CHI. The analog circuits includes, for example, circuits for processing an analog signal from a video camera, an analog/digital conversion circuit, a digital/analog conversion circuit and others.
In the logic merged memory, in order to simplify a fabrication process, internal components of logic circuit LG and memory circuit MK are fabricated in the same steps as much as possible.
In a case where memory circuit MK is a DRAM, word lines are configured according to a hierarchical word line scheme composed of main word lines and sub word lines, and the sub word lines are driven by sub word drivers.
When an operating frequency of logic circuit LG increases much more, however, an operating speed of memory circuit MK is also required to be higher with increase in the operating frequency of logic circuit MK. Therefore, in a case where sub word drivers are used, sub word lines SWL is required to be driven into a selected state at high speed. In order to drive sub word lines SWL into a selected state at high speed, possible consideration is that the division number on the memory sub blocks is increased to thereby decrease a length of a sub word line driven by one sub word driver. In this case, however, the number of sub word driver bands increases to increase a layout area of a memory array (a memory mat), thereby causing a problem of increase in chip area.
Furthermore, in the case where a word line shunt structure is applied, there arises a necessity of use of an interconnection layer different from a main word line and therefore, in the case where a metal interconnection line for use in forming a shunt is further to be provided, process steps of fabrication increase in number, resulting in a increased cost. Moreover, in the case where the number of metal interconnection layers increases, a difference in height between memory circuit MK and logic circuit LG becomes so large that correct patterning is ensured at a step portion (since a pattern variation occurs due to irregular reflection and so on of exposure rays in a photolithography step), which makes it difficult to arrange a new additional metal layer.